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首先是状态机.

对EDA来说,状态机是一个非常重要的部分.如果能灵活地运用状态机,那么写程序就可以游刃有余了!

状态机一般分为三种类型：
Moore型状态机：次态=f(现状，输入)，输出=f（现状）；
Mealy型状态机：次态=f(现状，输入)，输出=f（现状，输入）；
混合型状态机。

Moore型与Mealy型两种状态机的不同点在于，Moore型状态机的输出信号是直接由状态寄存器译码得到，而Mealy型状态机则是以现时的输入信号结合即将变成次态的现态，编码成输出信号。

以下是我收藏的一些程序,让大家更深刻地了解!

莫尔型状态机
library ieee;
use ieee.std_logic_1164.all;

entity moore2 is port(
        clk, rst:       in std_logic;
        id:             in std_logic_vector(3 downto 0);
        y:              out std_logic_vector(1 downto 0));
end moore2;

architecture archmoore2 of moore2 is
        signal state: std_logic_vector(2 downto 0);
-- State assignment is such that 2 LSBs are outputs
constant state0: std_logic_vector(2 downto 0) := "000";
constant state1: std_logic_vector(2 downto 0) := "010";
constant state2: std_logic_vector(2 downto 0) := "011";
constant state3: std_logic_vector(2 downto 0) := "110";
constant state4: std_logic_vector(2 downto 0) := "111";
begin
moore: process (clk, rst)
        begin
                if rst='1' then
                        state <= state0;
                elsif (clk'event and clk='1') then
                        case state is

                                when state0 =>
                                        if id = x"3" then
                                                state <= state1;
                                        else
                                                state <= state0;
                                        end if;
                                when state1 =>
                                        state <= state2;
                                when state2 =>
                                        if id = x"7" then
                                                state <= state3;
                                        else
                                                state <= state2;
                                        end if;
                                when state3 =>
                                        if id < x"7" then
                                                state <= state0;
                                        elsif id = x"9" then
                                                state <= state4;
                                        else
                                                state <= state3;
                                        end if;
                                when state4 =>
                                        if id = x"b" then
                                                state <= state0;
                                        else
                                                state <= state4;
                                        end if;
                                when others =>
                                        state <= state0;
                        end case;
                end if;
        end process;

--assign state outputs (equal to state std_logics)

y <= state(1 downto 0);
end archmoore2;



library ieee;
use ieee.std_logic_1164.all;

entity moore1 is port(
        clk, rst:       in std_logic;
        id:             in std_logic_vector(3 downto 0);
        y:              out std_logic_vector(1 downto 0));
end moore1;

architecture archmoore1 of moore1 is
        type states is (state0, state1, state2, state3, state4);
        signal state: states;
begin
moore: process (clk, rst)  --this process defines the next state only
        begin
                if rst='1' then
                        state <= state0;
                elsif (clk'event and clk='1') then
                        case state is
                                when state0 =>
                                        if id = x"3" then
                                                state <= state1;
                                        else
                                                state <= state0;
                                        end if;
                                when state1 =>
                                        state <= state2;
                                when state2 =>
                                        if id = x"7" then
                                                state <= state3;
                                        else
                                                state <= state2;
                                        end if;
                                when state3 =>
                                        if id < x"7" then
                                                state <= state0;
                                        elsif id = x"9" then
                                                state <= state4;
                                        else
                                                state <= state3;
                                        end if;
                                when state4 =>
                                        if id = x"b" then
                                                state <= state0;
                                        else
                                                state <= state4;
                                        end if;
                        end case;
                end if;
        end process;

--assign state outputs concurrently;
y <= "00" when (state=state0) else
     "10" when (state=state1 or state=state3) else
     "11";
end archmoore1;

米勒型状态机

library ieee;
use ieee.std_logic_1164.all;

entity mealy1 is port(
        clk, rst:       in std_logic;
        id:             in std_logic_vector(3 downto 0);
        y:              out std_logic_vector(1 downto 0));
end mealy1;

architecture archmealy of mealy1 is
        type states is (state0, state1, state2, state3, state4);
        signal state: states;
begin
moore: process (clk, rst)
        begin
                if rst='1' then
                        state <= state0;
                        y <= "00";
                elsif (clk'event and clk='1') then
                        case state is
                                when state0 =>
                                        if id = x"3" then
                                                state <= state1;
                                                y <= "10";
                                        else
                                                state <= state0;
                                                y <= "00";
                                        end if;
                                when state1 =>
                                        state <= state2;
                                        y <= "11";
                                when state2 =>
                                        if id = x"7" then
                                                state <= state3;
                                                y <= "10";
                                        else
                                                state <= state2;
                                                y <= "11";
                                        end if;
                                when state3 =>
                                        if id < x"7" then
                                                state <= state0;
                                                y <= "00";
                                        elsif id = x"9" then
                                                state <= state4;
                                                y <= "11";
                                        else
                                                state <= state3;
                                                y <= "10";
                                        end if;
                                when state4 =>
                                        if id = x"b" then
                                                state <= state0;
                                                y <= "00";
                                        else
                                                state <= state4;
                                                y <= "11";
                                        end if;
                        end case;
                end if;
        end process;

end archmealy;

带莫尔/米勒输出的状态机


library ieee;
use ieee.std_logic_1164.all;

entity mealy1 is port(
        clk, rst:       in std_logic;
        id:             in std_logic_vector(3 downto 0);
        w:              out std_logic;
        y:              out std_logic_vector(1 downto 0));
end mealy1;

architecture archmealy1 of mealy1 is
        type states is (state0, state1, state2, state3, state4);
        signal state: states;
begin
moore: process (clk, rst)
        begin
                if rst='1' then
                        state <= state0;
                elsif (clk'event and clk='1') then
                        case state is
                                when state0 =>
                                        if id = x"3" then
                                                state <= state1;
                                        else
                                                state <= state0;
                                        end if;
                                when state1 =>
                                        state <= state2;
                                when state2 =>
                                        if id = x"7" then
                                                state <= state3;
                                        else
                                                state <= state2;
                                        end if;
                                when state3 =>
                                        if id < x"7" then
                                                state <= state0;
                                        elsif id = x"9" then
                                                state <= state4;
                                        else
                                                state <= state3;
                                        end if;
                                when state4 =>
                                        if id = x"b" then
                                                state <= state0;
                                        else
                                                state <= state4;
                                        end if;
                        end case;
                end if;
        end process;

--assign moore state outputs;
y <= "00" when (state=state0) else
     "10" when (state=state1 or state=state3) else
     "11";
--assign mealy output;
w <= '0' when (state=state3 and id < x"7") else
     '1';
end archmealy1;

以下是基本语法:

基本语法是写程序的基本元素,只有把基础打好才能更向一层楼.

加法器：generate语句的应用

library IEEE;
use IEEE.Std_logic_1164.all;

ENTITY addn IS
   GENERIC(n : POSITIVE := 3);   --no. of bits less one
   PORT(addend, augend : IN BIT_VECTOR(0 TO n);
         carry_in : IN BIT; carry_out, overflow : OUT BIT;
         sum : OUT BIT_VECTOR(0 TO n));
END addn;

ARCHITECTURE generated OF addn IS
   SIGNAL carries : BIT_VECTOR(0 TO n);
BEGIN
addgen : FOR i IN addend'RANGE
   GENERATE
      lsadder : IF i = 0 GENERATE
         sum(i) <= addend(i) XOR augend(i) XOR carry_in;
         carries(i) <= (addend(i) AND augend(i)) OR
                       (addend(i) AND carry_in) OR
                       (carry_in AND augend(i));
         END GENERATE;
      otheradder : IF i /= 0 GENERATE
         sum(i) <= addend(i) XOR augend(i) XOR carries(i-1);
         carries(i) <= (addend(i) AND augend(i)) OR
                        (addend(i) AND carries(i-1)) OR
                        (carries(i-1) AND augend(i));
         END GENERATE;
   END GENERATE;
   carry_out <= carries(n);
   overflow <= carries(n-1) XOR carries(n);
END generated;

计数器：generate语句的应用

library ieee;
use ieee.std_logic_1164.all;

entity tff is
   port(clk, t, clear : in std_logic; q : buffer std_logic);
end tff;

architecture v1 of tff is
begin
   process(clear, clk)
   begin
      if clear = '1' then
         q <= '0';
      elsif rising_edge(clk) then
         if t = '1' then
            q <= not q;
         else
            null;
         end if;
      end if;      
   end process;
end v1;



library ieee;
use ieee.std_logic_1164.all;

entity bigcntr is
   generic(size : positive := 32);
   port(clk, clear : in std_logic;
         q : buffer std_logic_vector((size-1) downto 0));
end bigcntr;

architecture v1 of bigcntr is

   component tff is
      port(clk, t, clear : in std_logic; q : buffer std_logic);
   end component;

   signal tin : std_logic_vector((size-1) downto 0);

begin

   genttf : for i in (size-1) downto 0 generate
      ttype : tff port map (clk, tin(i), clear, q(i));
   end generate;

   genand : for i in 0 to (size-1) generate
      t0 : if i = 0 generate
         tin(i) <= '1';
      end generate;
      t1_size : if i > 0 generate
         tin(i) <= q(i-1) and tin(i-1);
      end generate;
   end generate;

end v1;

计数器：GENERIC语句的应用

LIBRARY ieee;
USE ieee.Std_logic_1164.ALL;
USE ieee.Std_logic_unsigned.ALL;

ENTITY cntrnbit IS
        GENERIC(n : Positive := 8);
        PORT(clock, reset, enable : IN Std_logic;
             count : OUT Std_logic_vector((n-1) DOWNTO 0));
END cntrnbit;

ARCHITECTURE v1 OF cntrnbit IS
        SIGNAL count_int : Std_logic_vector((n-1) DOWNTO 0);
BEGIN

        PROCESS
        BEGIN
                WAIT UNTIL rising_edge(clock);
                IF reset = '1' THEN
                        count_int <= (OTHERS => '0');
                ELSIF enable = '1' THEN
                        count_int <= count_int + 1;
                ELSE
                        NULL;
                END IF;
        END PROCESS;
        count <= count_int;
END v1;

计数器：wait语句的应用

library ieee;
use ieee.std_logic_1164.all;

ENTITY cntr3 IS
   PORT(clock : IN BIT; count : OUT NATURAL);
END cntr3;

ARCHITECTURE using_wait OF cntr3 IS
BEGIN
   PROCESS
   BEGIN
      --WAIT UNTIL (clock'EVENT AND clock = '1');
      WAIT UNTIL clock = '1';
      count <= 0;
      --WAIT UNTIL (clock'EVENT AND clock = '1');
      WAIT UNTIL clock = '1';
      count <= 1;
      --WAIT UNTIL (clock'EVENT AND clock = '1');
      WAIT UNTIL clock = '1';
      count <= 2;
   END PROCESS;
END using_wait;